Power-gating techniques generally involve shutting off or reducing voltage that is supplied to certain electronic circuit component(s) when such electronic component(s) are not in use, such as in a sleep or standby mode or otherwise idle mode.
Some power-gating techniques provide a transistor between a main power network (such as a Vcc supply voltage) and the power network (VccG or gated Vcc supply voltage) of a logic block or other load having the electronic component(s). The transistor operates as a power-gate transistor, such that the power-gate transistor operates as a switch that couples the Vcc supply voltage to the VccG supply voltage during a full/normal operational mode to thereby provide the Vcc voltage level to the logic block, and the transistor decouples the Vcc supply voltage from the VccG supply voltage during the idle mode to thereby reduce power consumption or leakage current consumption.
However, the power-gate transistor is often large in size, and so switching the power-gate transistor OFF (to decouple the Vcc supply voltage from the VccG supply voltage) and ON (to couple the Vcc supply voltage to the VccG supply voltage) consumes energy itself. Accordingly, if the idle mode is short in time duration and the power-gate transistor is turned OFF for a short period of time (during the idle mode) and then turned ON again, the energy consumed for turning the power-gate transistor OFF and ON may be larger than the leakage current savings. To reduce the energy consumption, some conventional power-gating techniques refrain from using the power-gate transistor during short idle periods.
Hence, switching power-gate transistors OFF and ON may reduce their efficiency and limit their usage.